Referring to FIG. 1, there is shown a prior art FIFO circuit 100. FIFO circuit 100 includes a write data FIFO 102 coupled to a write data bus and a read data FIFO 104 coupled to a read data bus. An output multiplexer (MUX) 106 under the control of a data select signal 108 controls which data to present at the output (DATA_OUT) 110 of the MUX 106. FIFO circuit 100 is typically used for applications where data from both read and write data busses need to be captured, buffered and then presented to an output interface.
Considering an application where the data bus width is 64 bits wide and the buffering requirement is 16 data words in all, by using FIFO circuit 100 both the write data FIFO 102 and the read data FIFO 104 have to have a width of 64 bits and a depth of 16. Since both the write data FIFO 102 and the read data buffer 104 have to be the same size, this may lead to under utilization of memory in the FIFO's in situations were the amount of data coming into one of the FIFO's is less than that coming into the other FIFO. The FIFO circuit 100 also requires one or more multiplexers having a large fan-in (both the write 102 and read 104 both FIFOs each require a 16:1 mux), this large fan-in has the potential of taking away a big margin of timing. To solve the timing problem, often the outputs are registered, causing the design area to be increased and performance to be reduced by a latency of one extra clock cycle.